Call for Topics across Seven Forums

Please select the appropriate forum based on your research or industry area when submitting your topic.

Each track welcomes both academic research contributions and industrial deployment reports. Work previously presented at peer-reviewed venues (e.g., ISCA, MICRO, HPCA, ASPLOS, DAC, PLDI/CGO) is explicitly welcome; the program committee will deliberately program research results alongside deployment experience within sessions.

1. Track on Artificial Intelligence

Scope: Focuses on RISC-V’s role across the full AI computing stack — from ISA standardization of matrix / vector extensions, compilers and operator libraries, to AI frameworks and runtimes, and on to system integration of cloud clusters and heterogeneous edge deployment. Sessions should balance standardization progress with real product / deployment cases. Architecture and compiler research on matrix / vector acceleration — including work published at peer-reviewed venues — is equally in scope.

2. Track on Datacenter / HPC

Scope: Focuses on platform-level deployment of application-class RISC-V in datacenter and high-performance computing: server SoC and platform specifications; firmware and boot (UEFI / ACPI / SBI); memory and interconnect (including CXL); virtualization and cloud-native orchestration; confidential computing and trusted execution; HPC parallel frameworks and scalability. Research contributions on server-class microarchitecture, memory and interconnect architecture, and system software for scalable RISC-V systems are equally in scope.

3. Track on Software Ecosystem

Scope: Covers the general-purpose software ecosystem from toolchains, kernel, and firmware to distributions and upper-layer runtimes — the horizontal layer underpinning every vertical application, as well as managed / language runtimes (JVM, V8, .NET, Python, Rust, Go); JITs; debugging and performance-analysis toolchains; multi-distribution and software-package ecosystems. Focuses on portable software enablement and ecosystem maturity. Research on compilation techniques, runtime systems, and performance analysis — including previously published academic work — is equally in scope.

4. Track on Design and Verification

Scope: Covers the full design-verification chain — from microarchitecture and RTL design and agile methodologies (Chisel / SpinalHDL), to pre-silicon / formal verification, conformance (compliance) testing, prototyping (FPGA / simulation), and tape-out. Also covers EDA tooling, with particular emphasis on open-source EDA and the open-source RISC-V core ecosystem, along with conformance-oriented verification methodology.

5. Track on Automotive, Industrial & Robotics

Scope: Targets RISC-V deployment in safety-critical and real-time embedded domains, covering automotive E/E architectures, industrial control, robotic motion and perception, the low-altitude economy, and aerospace. Functional safety (ISO 26262 / IEC 61508), real-time determinism, and safety-critical certification, as well as automotive-grade software stacks and AUTOSAR adaptation.

6. Track on Embedded, IoT & Smart Hardware

Scope: Targets resource-constrained, cost-sensitive embedded and IoT volume-production scenarios, covering MCU-class RISC-V; RTOS and bare-metal software; low power and power management; wireless connectivity; on-device AI (TinyML); device security and trusted boot; and mass production and supply chain, as well as the latest industrialization progress of various consumer electronic products.

7. Track on Industry-Academia Collaboration, Innovation & Entrepreneurship

Scope: Covers RISC-V talent development and curriculum building; frontier research at universities and research institutes; open-source community and standards-body collaboration; and the startup and investment ecosystem.

Submission Link

https://cfp2026.riscv-summit-china.org/rvsc2026/cfp

For questions, please contact the organizing committee: risc-v_summit_2026@rioslab.org