Posters will be displayed in Orchid Hall on October 19–20, 2026. Find your poster number below and put up your poster at the corresponding numbered position. Each accepted poster has one assigned position.
Please print your poster in advance and bring it to the venue for self-setup. The finished size is 91 cm (width) × 122 cm (height); the organisers do not provide printing services.
View the Orchid Hall floor plan and numbered poster positions
| Position | Submission code | Poster title | Authors |
|---|---|---|---|
| H01 | UBABJN | High-Bandwidth Memory Access Optimization for the Matrix Module of the XiangShan AI Processor | Huizhe Wang |
| H02 | WV98DF | A Proposal for RISC-V Vector Complex-Number Floating-Point Instruction Extensions | Xudong Liu |
| H03 | WMTJPN | Portable NTrace Debug | Ken Gildersleeve |
| H04 | YNNXUC | openKylin RISC-V+AI: From Architecture Support to Intelligent Application Deployment | Zhuoheng Li |
| H05 | QG7PSZ | RISC-V IOMMU Two-Stage Translation: A Full-Stack Implementation from QEMU to the Linux Kernel | Gong Shuai |
| H06 | NPXVMU | Practices of Formal Verification in RISC-V Microarchitecture Verification | TAO WANG |
| H07 | HDHUU3 | ZhiQian Platform: An Intelligent Software Migration Delivery Platform for RISC-V and Domestically Developed Computing Power | Guo, Minxin |
| H08 | FF39LK | Design and Extreme Performance Optimization of the ISA-L EC Storage Acceleration Library for RISC-V | Shuo Lv |
| H09 | Z3TH9V | A Self-Evolving System for Chip Verification Agents Based on Experience Closed-Loop Distillation, and Empirical Evidence of Its Effectiveness | Yingying wu |
| H10 | CXYJAU | deepin-ports on RISC-V: Practice and Progress | Chang Yang |
| H11 | WNKKRK | Evolution of Automotive-Grade RISC-V Debug Technology: Shift-Left, Heterogeneous, and System-Level Trace | Eric Liu |
| H12 | MQVDHH | From Choosing a CPU to Defining a CPU: Practical Explorations of RISC-V Reshaping Storage-Control Computing | Yitong Liu |
| H13 | VEM8X3 | Toward the AI Era: The "Lighting-Up" Program and New Practices in the RISC-V Talent Ecosystem | LiMeng |
| H14 | T9TAVT | RISC-V Adaptation and Optimization of the Large Model Inference Stack: Engineering Practice and Ecosystem Gap Analysis | Shaocong Wu |
| H15 | WT7N3F | Sail-RISCV-WASM: A Browser-Native RISC-V Toolchain and Debug Workbench | Mingzhu Yan; Yunxiang Luo |
| H16 | PVBHCB | Same Model, Different Answers: Numerical Semantics of RISC-V Matrix Extensions and On-Device AI Reliability | Wei Liu |
| H17 | SZX73D | Hardware-Software Co-Design: Building a High-Performance RISC-V Foundational Library Software Ecosystem | Leacy Lan |
| H18 | 8CYP3V | RISC-V High-Performance Computing Security Protection System | Peng Wu |
| H19 | YMWTNK | A Trustworthy Benchmarking Methodology for LLM Agents in Chip Verification | Cheng Gou |
| H20 | 8XCNJ8 | XuanTie RISC-V IP: A Programmable Foundation for On-Device NPU | Zhuang Shen |
| H21 | Y3RH39 | XuanTie RISC-V Empowering Robotics: Full-Stack Capability and Core Algorithm Optimization | wang kun |
| H22 | MAKWCY | Joint Motor Control Practice Based on a RISC-V Architecture DSP | Wuqi Wang |
| H23 | NTUTHN | An Automotive-Grade Safety Core Featuring Ultra-Low Interrupt and Nested Interrupt Latency | Paul Ku |
| H24 | H3UT9K | The State of RISC-V Graphics Drivers in 2026: A Linux Distribution Perspective | Icenowy Zheng |
| H25 | GC7DBC | A Streaming Verification Approach for High-Performance RISC-V Processors | xiaoxiao |
| H26 | DBMPTZ | PRISM: Intelligent RISC-V Hardware–Software Configuration via Large Language Models | Xing Cui |
| H27 | CD3KH8 | Dayan NPU: A Tensor-Native Open-Source RISC-V AI Processor | Guanglin Xu |
| H28 | TJLNAC | RISC-V in China: A Three-Track Practice of Industry-Academia Foundation Building, Joint Standards Development, and Ecosystem Going Global | Jerry Tan |
| H29 | QMLTEA | A Simulator-RTL Alignment Methodology for High-Performance RISC-V Processors | ZhenHao |
| H30 | GQMPAY | "YuQuan": A High-Performance Memory Controller IP | Tianyue Lu |
| H31 | QA7RXX | From PyTorch to vLLM: Support and Optimization for Large Model Inference on Multi-Die RISC-V | wenmeng zhang |
| H32 | PRPQYZ | RVFlow: Full-Stack Adaptation and RVV Acceleration of a Vector Database for RISC-V | Liuyudong |
| H33 | V37YKB | Empowering Intelligent Vehicles: Delivery Practice of RISC-V Automotive-Grade System Software from Verification to Mass Production | Pengpeng Tang |
| H34 | WXWRRC | Application of High-Performance RISC-V AI CPUs in Embodied Robots | Anju.Chan |
| H35 | MX8DHD | Firmware Testing Practice for Standard RISC-V Server Platforms Based on openRuyi | Xiang W |
| H36 | RGSYLN | Full-Stack Security for XiangShan: From Processor Execution to System-Level Protection | yuanmiaomiao |
| H37 | KRJEER | A Cross-Side Fuzzing Approach for the RISC-V KVM Kernel Module | Jiakai Xu |
| H38 | NPCYBY | The Software Cornerstone: Practice in Building a High-Performance RISC-V Compiler Ecosystem | Ziyang Zheng |
| H39 | L7GPMC | A Hybrid RISC-V Security Verification Platform for XiangShan Processor | Haichen Zhou |
| H40 | X7AFZP | Porting Unikraft, a Lightweight Isolated Execution Environment for RISC-V MicroVM/Sandbox | ZhangZheng |
| H41 | ZDDZTV | From Hack to Specification: FDT-Based Boot Flow and Generic Image Practice for RISC-V Platforms | Hangfan Li |
| H42 | HS3B73 | C950 RISC-V Server Platform BIOS Capability Overview | Evan |
| H43 | RNEQDZ | Integration and Standardization Gaps in RISC-V SoC I/O Isolation | Haoyuan Liu |
| H44 | HJ738T | Automatic Test generation from Sail Golden Model | Jahanzeb Khalid |
| H45 | M9REYU | AI-Driven Testing of RISC-V GUI Applications | Yunxiang Luo; Weilin Cai; Mingzhu Yan |
| H46 | PBBXCQ | Exploration and Practice of an Automated Porting Workflow for the RISC-V Ecosystem Based on Large Model Technology | Jason Peng |
| H47 | UMKLSX | The RISC-V Binary Translation Open Source Ecosystem: Box64 and Felix86 | Mark Zhuang; Zhijin Zeng |
| H48 | XWTHRF | OpenHW CVA6 in Full View: Architectural Positioning, Recent Progress, and Future Roadmap | Junchao Chen |
| H49 | EENBEJ | DigitalBridge: A High-Performance Binary Translation System for RISC-V | Li Gao |
| H50 | V3DEW7 | RuyiAI: A RISC-V Native AI System Software Stack | Hongbin Zhang |
| H51 | AYRLS8 | From Fragmentation to Systematization: RISC-V Course Quality Assessment and Systematic Reconstruction | zhangfuyuan; Yunxiang Luo |
| H52 | 9KW8VW | An AI Heterogeneous Computing Platform Based on the Yosemite RISC-V SoC: Wormhole Enablement and Large Model Inference Practice | Dong Xie |
| H53 | GPJMWV | SMT-2 Modeling, Performance Analysis, and Optimization of KunMingHu V3 Based on XS-GEM5 | Xingyu Du |
| H54 | BZ9TQK | Ruyi Package Manager: An Integrated, All-in-One Development Environment Built for RISC-V Developers | Weilin Cai; Yunxiang Luo |
| H55 | Y9TN77 | A Coverage Convergence Method for Chip Verification Based on RTL Semantics and Coverage Feedback | Fangyuan Song |
| H56 | LXSMDT | Pulsar: Cross-platform external traffic generator for CPU stress testing | Gayathri Vadhyan; Ganesh Valliappan; Sajosh Janarthanam |
| H57 | EGH38V | Eclipse Atesor: Deterministic-First Agentic Framework for RISC-V Software Porting | Akif Ejaz |
| H58 | 9ZGRWN | Building the Open Source Ecosystem for RISC-V | Zhe Yi |
| H59 | NMCPP9 | Functional Verification Strategy of the CORE-V Floating-Point Unit (CVFPU) for RISC-V cores | Ihsane Tahir, Flo Wohlrab |
| H60 | UR9DUY | RISC-V Confidential Computing: From Standard to Silicon Implementation | Baolong Duan |
| H61 | PFLVCZ | XuanTie's Progress on the RISC-V Compiler | Cooper Qu |
| H62 | 89ZCA3 | RuyiTuner: An LLVM Tuning Tool Based on Optimization Synergy Analysis | Ningning Shi |
| H63 | CPFSJE | Domestically Developed High-Performance RISC-V MCU: Building the Core Foundation Platform for Robot Motion Control | Zhendong Fei |
| H64 | JQLT8V | An Efficient Method for Applying the RISC-V Sail Model to Chip Verification | Mingzhu Yan; Yunxiang Luo |
| H65 | GTLLCU | AI Driven Module-Level Specification-to-Code Extraction and Mapping | piyan |
| H66 | 7M38VD | Strengthening the Foundation and Optimizing Layer by Layer: Building the RISC-V Database Software Ecosystem | Xiaoqiang Jiao |
| H67 | FHHUPX | A Project-Level Software Source Code Migration Agent for RISC-V | JIAXIN ZHU |
| H68 | MPWTYM | Weft: A High-Performance RISC-V Operator Compiler for Encoding-Aware Hierarchical Numerical Implementation Abstraction | zhenyu zhang |
| H69 | PFWFMS | Toward the RISC-V Server Platform Specification: Progress and Plans for openEuler on RISC-V | Jiacheng Zhou |
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