RISC-V SUMMIT CHINA 2026

Agenda

Agenda Overview

DateTimeProgram
SundayOctober 189:00–12:30RISC-V Member Day | Workshops | Community ExchangeNarcissus Hall · 6F
9:30–18:00GPGPU Session | RISC-V Member DayTulip Hall · 6F
9:30–18:00AI for RISC-VRose Hall 1 · 5F
9:30–18:00XiangShan Processor SessionRose Hall 2 · 5F
MondayOctober 199:00–12:20The 6th RISC-V Summit China Opening CeremonyPlum Blossom Hall · 5F
13:30–17:40The 6th RISC-V Summit China Main ForumPlum Blossom Hall · 5F
10:20–11:20Demo Talk (morning)
15:30–16:15Demo Talk (afternoon)
TuesdayOctober 209:00–17:45Artificial Intelligence ForumJasmine Hall · 6FCo-chairs: David Chen (Stream Computing); Zhong Su (DAMO Academy)
9:00–17:45Datacenter and High-Performance Computing ForumNarcissus Hall · 6FCo-chairs: Ray C.C. Cheung (City University of Hong Kong); Ning He (ESWIN Computing)
9:00–17:45Software Ecosystem ForumPeony Hall · 5FCo-chairs: Sheng Qu (Institute of Software, CAS); Samuel Li (RISCstar)
9:00–17:45Embedded, IoT and Smart Hardware ForumChrysanthemum Hall · 5FCo-chairs: Zhenbo Hu (Nuclei); Derek Zhang (HiSilicon)
9:00–17:45Chip Design & Verification ForumRose Hall 1 · 5FCo-chairs: Dan Tang (Beijing Institute of Open Source Chip); Charlie Su (Andes Technology)
9:00–12:30Industry-Academia Collaboration, Innovation and Entrepreneurship ForumRose Hall 2 · 5FCo-chairs: Ming Liu (RIOS Lab); Xuan Yang (Linux Foundation APAC)
13:30–17:45Automotive, Industrial and Robotics ForumRose Hall 2 · 5FCo-chairs: Thomas Xu (StarFive Tech); Yong Yang (WCH)
10:15–10:30Demo TalkSunflower Hall · 5F
WednesdayOctober 219:00–17:10RISC-V Hong Kong DayRoom B-101 · CityUHK ICP

Sunday, October 18

Narcissus Hall · 6FRISC-V Member Day | Workshops | Community Exchange

TimeSession
9:00–9:30Member Q&A with the RISC-V CEO (For RISC-V members)
9:30–11:00CSC meeting (For RISC-V members)
11:00–12:30Seminar on Matrix Extension Instruction Sets and Software AbstractionVideo conference

Tulip Hall · 6FGPGPU Session | RISC-V Member Day

GPGPU session organizer: Tsinghua University

TimeSession
9:30–12:30Ventus Open-source GPGPU: Latest Updates and Hands-on Practice
13:30–16:00SPMP Workshop
16:00–18:00Certification Committee (For RISC-V members)

Rose Hall 1 · 5FAI for RISC-V

Organizers: Stream Computing, ICT CAS, ISCAS, 10xEngineers

TimeSession
9:30–12:30Part 1: Full-stack Practice from Pre-silicon RISC-V Chip Prototypes to AI Software
13:30–15:30Part 2: RISC-V AI Practice with the RuyiAI System Software Stack: From RVV to AME
15:30–18:00Part 3: Trustworthy AI-generated Verification: Validating Protocol Checkers through Mutation Testing

Rose Hall 2 · 5FXiangShan Processor Session

Organizers: ICT CAS, Beijing Institute of Open Source Chip

TimeSession
9:30–12:30Part 1: High-performance Architecture Evolution and Industrial Verification Practice for XiangShan
13:30–15:30Part 2: UCAgent Practice with the XiangShan Processor
15:30–18:00Part 3: RISC-V Processor IP Security Verification Platform

Monday, October 19

Detailed agenda coming soon.

Tuesday, October 20

Jasmine Hall · 6FArtificial Intelligence Forum

Co-chairs: David Chen (Stream Computing); Zhong Su (DAMO Academy)

TimeSession
9:00–9:15Next Generation of Extensible DSP for AIRocky Zhang · Cadence Design Systems
9:15–9:30An Open Matrix Architecture for AI: RISC-V AME Standardization and Hardware Design PracticeRuiqi Xie · Alibaba Damo Academy
9:30–9:45Advancing RISC-V AI Architecture: A Deep Dive into SiFive’s Second-Generation Intelligence FamilyZhengwei Guo · SiFive
9:45–10:00LLM-Assisted, Auditable Microarchitecture-Aware Scheduling Search for RVVHeng-Kuan Lee · Andes Technology
10:00–10:15Intelligence will be everywhere.Alan Li · MIPS, by GF
10:15–10:45Coffee Break
10:45–11:00Deploying Large Models on an In-House RISC-V AI Core and a Verification Methodology for Matrix ExtensionsXiaogeng Wang · Beijing ESWIN Computing Technology Co., Ltd.
11:00–11:15RISC-V AI Operator Library: Building a High-Performance Open Intelligent Computing EcosystemJian Zhang · ZTE Corporation
11:15–11:30Design of the XiangShan "Badaling" AI IP and Its Companion Software StackMingjin Gao · Institute of Computing Technology, Chinese Academy of Sciences
11:30–11:45Baltoro: A RISC-V-First AI Compiler StackAdeel Ahmad · 10xEngineers
11:45–12:00Tile-Level Parallel Programming Model and Compiler-Runtime Co-Design for Homogeneous Converged AI-CPUsJingHui Huang · SpacemiT Technology Co Ltd
12:00–13:30Lunch
13:30–13:45Unlocking AI in Cloud Computing: Accelerating RAG Workloads with RISC-V CPUsYunFei Zhou / Yizhe Lyu · Alibaba DAMO Academy
13:45–14:00Vectra RVX: Extending RISC-V into Programmable DSP and AI CoprocessingGeorge Wall · Cadence Design Systems
14:00–14:15High-Bandwidth L2 Cache Design for Large Model Inference on AI CPUsXi Chen · 中国科学院计算技术研究所；北京开源芯片研究院
14:15–14:30Nuclei AI-Specific RISC-V Processor IPNeil Fan · Nuclei System Technology
14:30–14:45RV-Sparse: RISC-V Vector Acceleration for Sparse General Matrix-Matrix MultiplicationTalha Ahmed · Micro Electronics Research Lab (MERL), UIT University
14:45–15:00Practice of Deep Learning Compilation Agents on RISC-V NPUZhengyu Xiao · Stream Computing
15:00–15:15Three Matrix Extensions, One Software Stack: Where IME, VME and AME Fit in RISC-VPhilipp Tomsich · VRULL GmbH
15:15–15:30RISC-V Processor Solutions for Embodied AI and Physical AICharlie Su · Andes Technology
15:30–15:45how to run LLM and other models on RISC-VItai Yarom · Akeana
15:45–16:00Agent-Assisted Adaptation of New Large Models to RISC-V AcceleratorsJinfeng Hu · Shanghai Jiaotong University
16:00–16:30Coffee Break
16:30–16:45Reshaping the Future of Open-Source AI Computing: From OS to vLLM — Co-Building the Foundation of the RISC-V AI EcosystemWei Fu · Red Hat Limited
16:45–17:00RVV-Accelerated KV Cache Compression for Cold-Tier Memory on Yosemite SoCXiaoxuan Liu · Corelab tech Ltd.
17:00–17:15From Single-Box Intelligence to Multi-Box Federation: Architecture and Practice of RISC-V Agent InfrastructureZhiyuan Liang · China Telecom Research Institute
17:15–17:30RISC-V Adaptation and Optimization of the Large Model Inference Stack: Engineering Practice and Ecosystem Gap AnalysisShaocong Wu · ZTE Corporation
17:30–17:45ZhiQian Platform: An Intelligent Software Migration Delivery Platform for RISC-V and Domestically Developed Computing PowerMinxin Guo · Beijing Research Institute, China Telecom Corporation Limited (Research Institute of China Telecom)

Narcissus Hall · 6FDatacenter and High-Performance Computing Forum

Co-chairs: Ray C.C. Cheung (City University of Hong Kong); Ning He (ESWIN Computing)

TimeSession
9:00–9:15Evolving RISC-V Privileged Architecture Extensions for ServerQingwei Hu · ByteDance
9:15–9:30Lightning Talk1 RISC-V + AI-Native HPC: A New Technological Paradigm for the Agentic EraLongcang Tong · 深圳市中兴微电子技术有限公司
9:30–9:45When will RISC-V break through into mainstream HPC?Nick Brown · EPCC at the University of Edinburgh
9:45–10:00UltraRISC UR Series High-Performance Processor CoresJiang Jiang · 超睿科技（上海）有限公司
10:00–10:15Evolution of Domestic Standards for High-Performance Server PlatformsZhe Qiao · Institute of Software, Chinese Academy of Sciences
10:15–10:45Coffee Break
10:45–11:00Deepening General-Purpose and AI Computing: Industrial Application Practices of Sophgo’s High-Performance RISC-V ProcessorsXiaoxiao Kang · 厦门算能科技股份有限公司
11:00–11:15When Requirements Meet Open Source: KunMingHu V3 Requirements Engineering and the XiangShan Open Source Working GroupJian Zhang / Shunchao Hu / Tianzhi Chang · Beijing Institute of Open Source Chip
11:15–11:30AIA Extension Proposal for Agent Sandbox: SMSIC and IMSIC MRIFRen Guo · Alibaba Damo Academy
11:30–11:45DASICS - A Memory Safety Isolation Technology Based on RISC-V ProcessorsTianyue Lu · Institute of Computing Technology, Chinese Academy of Sciences
11:45–12:00Toward High-Performance RISC-V General-Purpose/AI Computing: SpacemiT's Full-Stack Technology Architecture and PracticeXiaolong Fei · SpacemiT Technology Co Ltd
12:00–13:30Lunch
13:30–13:45Unleashing RISC-V Vector Potential: Efficient Hardware-Software Co-Design and Practice from Instruction Set to Computing PowerJing Qiu · Alibaba Damo Academy
13:45–14:00High-Performance Computing: XiangShan — An Open-Source Computing Chip Solution for the AI EraJian Zhang / Shunchao Hu / Tianzhi Chang · Beijing Institute of Open Source Chip
14:00–14:15How Many Instructions Away Is RISC-V from the Data Center?Pengcheng Wang · ByteDance
14:15–14:30Efficient Video Encoding on RISC-V: Porting and Optimization Practice of x265Changsheng Wu · 深圳市中兴微电子技术有限公司
14:30–14:45Building a Server-Class Full-Stack Heterogeneous AI Inference Software Stack on the RISC-V PlatformStephen Xi · 武汉元石智算科技有限公司
14:45–15:00The World's First Full-Featured RISC-V Data Center Management ChipJay Zhou · 上海赛昉半导体科技有限公司
15:00–15:15Beyond PMP: Evaluating and Mitigating Memory Aliasing Attacks on RISC-V ProcessorsYicheng Zhong · Institute of Software, Chinese Academy of Sciences
15:15–15:30Akeana Alpine - building high-performance RVA23 ASICItai Yarom · Akeana
15:30–15:45One Kernel Per Cluster: Multikernel for Heterogeneous RISC-VCong Wang / Yanwei Huang · Multikernel Technologies / DeepComputing
15:45–16:00Vector Extension Design for General-Purpose High-Performance ComputingXuan Hu · Institute of Computing Technology, Chinese Academy of Sciences
16:00–16:30Coffee Break
16:30–16:45Design of the RISC-V Complex-Number Matrix Instruction SetXiaoxia Yao · China Mobile Research Institute
16:45–17:00Embody AI with LingCage: Tailored RISC-V Native VMM for Agentic WorkloadsRuoqing He · 灵可及（杭州）科技有限公司 ｜ LingCage
17:00–17:15Architectural Evolution of RISC-V Confidential Computing and Data Center Deployment PlanningQiang Li · Solutions Director, 北京瑞偲创新科技产业有限公司
17:15–17:30Development Opportunities for High-Performance RISC-V CPUs in the Agent EraHuaqing Li · 上海灵睿智芯计算技术有限公司
17:30–17:45High-Performance RISC-V Practice for AI Data CentersXiaobo Ye · Product Director, Guangdong LeapFive Technology Limited

Peony Hall · 5FSoftware Ecosystem Forum

Co-chairs: Sheng Qu (Institute of Software, CAS); Samuel Li (RISCstar)

TimeSession
9:00–9:15openRuyi: Building Public Infrastructure for the Forward-Looking Evolution of RISC-VJingwei Wang · Institute of Software, Chinese Academy of Sciences
9:15–9:30Fixed-Length Vectors for RVV: Types, Intrinsics, and ABIKito Cheng · SiFive
9:30–9:45Strengthening the Software Foundation and Accelerating Industry Deployment: How Linux Distributions Build a Thriving RISC-V EcosystemWei Fu · Red Hat Limited
9:45–10:00Evolution and Practice of the RISC-V Debug Toolchain Across the Full LifecycleCyan Tsao · Lauterbach China
10:00–10:15From Chip to Ecosystem: Full-Stack Practice of an Agent OS on RISC-VDong Xu · 进迭时空（杭州）科技有限公司
10:15–10:45Coffee Break
10:45–11:00RuyiRepo: Making RISC-V Software Ready to Use Out of the BoxGuanyu Liang · Institute of Software, Chinese Academy of Sciences
11:00–11:15XSCC: A High-Performance RISC-V CompilerLv Fang · Institute of Computing Technology, Chinese Academy of Sciences
11:15–11:30XuanTie Is Java-Ready: XuanTie CPU Contributions to OpenJDKLibing Huang · Alibaba Damo Academy
11:30–11:45RISC-V LLVM Stack Access Optimization for Large-Scale Program WorkloadsChenxi He · Beijing Institute of Open Source Chip
11:45–12:00ZTE BT: A High-Performance Binary Translation Tool for Running Applications Across ArchitecturesDavid Xie · 北京砺睿微电子科技有限公司
12:00–13:30Lunch
13:30–13:45RISC-V P-Extension: Performance, Validation, and Toolchain SupportHank Chang · SiFive
13:45–14:00Security Governance of RISC-V Open Source Foundational SoftwareTong Liu · Institute of Software, Chinese Academy of Sciences
14:00–14:15DigitalBridge+: High-Performance Binary Translation and Intelligent Migration for the RISC-V Application EcosystemMengyao Xie · Institute of Computing Technology, Chinese Academy of Sciences
14:15–14:30Building a Solid RISC-V Storage Foundation: Ceph Adaptation and Optimization in PracticeWen Lei · ZTE Corporation
14:30–14:45Making RISC-V + AI Easier to Use: A Parallel Programming Paradigm for Asynchronous Tensor ComputationYuanbo Wen · Institute of Computing Technology, Chinese Academy of Sciences
14:45–15:00Chimera: Transparent and High-Performance ISAX Heterogeneous Computing via Binary RewritingJiatai He · Institute of Software, Chinese Academy of Sciences
15:00–15:15Exploring a New Approach to Many-to-One Virtualization for the RISC-V ArchitectureTianlei Xiong · 上海交通大学计算机学院可扩展计算研究所
15:15–15:30RVA23, Meet Bao: Open-Source Static-Partitioning Virtualization on the SpacemiT K3Manuel Rodríguez · University of Minho
15:30–15:45Open-Source GPU Drivers on RISC-VZheng Zhang · Imagination Technologies
15:45–16:00From Boot to RAS: Machine-Checkable Verification for RISC-V SBI FirmwareYeqian Yang · 山东大学
16:00–16:30Coffee Break
16:30–16:45Building a Trusted Execution Environment Based on RISC-V WorldsYu-Chien Lin · SiFive
16:45–17:00Gaps in RISC-V mainline Linux - a PCIe case study on K1, JH7110 and EIC7700 SoCsAli Tariq · 10xEngineers
17:00–17:15Porting Apache ORC to the RISC-V Platform and RVV Vector Optimization in PracticeChangbao Zhan · 深圳市中兴微电子技术有限公司
17:15–17:30Building the RISC-V Trace Software Ecosystem: N-Trace Software Stack Practice and Upstreaming Contributions Based on the K3 PlatformZane Leung / Mark Zhuang · 进迭时空（珠海）科技有限公司
17:30–17:45Maturity Assessment of the RISC-V Foundational Software Ecosystem for Data CentersChenchen Ji · Institute of Software, Chinese Academy of Sciences

Chrysanthemum Hall · 5FEmbedded, IoT and Smart Hardware Forum

Co-chairs: Zhenbo Hu (Nuclei); Derek Zhang (HiSilicon)

TimeSession
9:00–9:15Design and Application of the ESS-E Embedded Secure Trusted Execution Environment SolutionJerry Chai · Beijing ESWIN Computing Technology Co., Ltd.
9:15–9:30RISC-V Empowering High-Performance Computer Peripherals: Technical Practice and Innovation from Chip to ProductOren Yu · 南京沁恒微电子股份有限公司
9:30–9:45From Customization to Generality: Practice and Reflections on Building the RISC-V Embedded EcosystemAllan He · Embedded Systems Association
9:45–10:00Fully Autonomous Safety-Critical Processor for AviationJianrui He · 中国航空工业集团西安飞行自动控制研究所
10:00–10:15RISC-V + OpenHarmony Powering the Future of On-Device AI ChipsDerek Zhang · RISC-V工委会
10:15–10:45Coffee Break
10:45–11:00From "Model onto the Chip" to "Agent Entering the Scene": RT-Thread's Full-Stack RISC-V On-Device AI PracticeBingru Zhang · RT-Thread
11:00–11:15T0 Ecosystem Chip: A Full-Scenario RISC-V Embedded Development PlatformHuaqi Fang · Nuclei System Technology
11:15–11:30Progress Report from the Joint OR Working Group of the OpenHarmony Community and the Ruyi Community — Building a Converged OpenHarmony + RISC-V EcosystemSenwen Zheng · Institute of Software, Chinese Academy of Sciences
11:30–11:45Building TrustZone-like TEEs for RISC-V MCUs: From ISA Primitives to PSA-Compatible Secure ServicesHuizhe Zheng · OSYX Technologies
11:45–12:00Mastering RISC-V Software Development Complexity: Advanced Debugging, Code Analysis, and Optimization Techniques in PracticeNicholas Zheng · IAR
12:00–13:30Lunch
13:30–13:45AI-Powered Tools for Easier Custom-Chip DesignRick Wang · MIPS by GF, A Global Foundries Company
13:45–14:00Medical Applications of AI Edge ComputingArron Lau · 暨南大学暨芯集成电路产业研究院
14:00–14:15Gaining runtime insights into a RISC-V target via System Bus AccessRyan Sheng · SEGGER Microcontroller China Co., Ltd.
14:15–14:30Qt for RISC-V Smart Hardware: Production-Grade HMI Deployment from MCU to Application ProcessorMacsen Wang · The Qt Company Ltd
14:30–14:45Unleashing Bonsai-27B: 1-bit LLM Inference on RISC-V Edge-Class Vector ProcessorsHung PeiHsiang · Andes Technology
14:45–15:00HBM Is Not All You Need: Efficient Disaggregated and Memory-heterogeneous LLM Serving with CrossServeZhixiang Wei · Shanghai Jiao Tong University
15:00–15:15ECOS Studio: RISC-V SoC Verification and Community Tape-out Practice Based on Open Source EDA, IP, and PDKHao Wang · Institute of Computing Technology, Chinese Academy of Sciences
15:15–15:30Software Verification in RISC-V Chip Mass ProductionLv Zheng · Beijing ESWIN Computing Technology Co., Ltd.
15:30–15:45From Assembly to Debugger: Building a Modern RISC-V Toolchain in RustTao Liu · Independent
15:45–16:00Strengthening the RISC-V Performance Evaluation Foundation: Test Case Contributions and Ecosystem Adaptation for Performance Evaluation ToolsRandy Wang · 中兴微电子
16:00–16:30Coffee Break
16:30–16:45KernelX: Agentic Kernel Generation for Custom RISC-V AI HardwareTaimur Ahmad / Adeel Ahmad / Nouman Amir · 10xEngineers
16:45–17:00If Every Chip Is Designed by AI in 2035 - It Can Only Start from an Open Source Core: An Open Source RISC-V Core Experiment Benchmarked Against ARM M7Yang Mu · CrossV开源社区
17:00–17:15VSCode IDE for RISC-V: An AI-Empowered Development Tool for RISC-VHuaqi Fang · Nuclei System Technology
17:15–17:30RISC-V Course Porting Methodology and RuyiSDK Ecosystem DevelopmentFuyuan Zhang / Yunxiang Luo · Intelligent Software Research Center, Institute of Software, Chinese Academy of Sciences / Institute of Software, CAS
17:30–17:45Harnessing the RISC-V Vector Extension: Practical RVV Optimization in GoJulian Zhu / Zhuo Meng · Institute of Software, Chinese Academy of Sciences

Rose Hall 1 · 5FChip Design & Verification Forum

Co-chairs: Dan Tang (Beijing Institute of Open Source Chip); Charlie Su (Andes Technology)

TimeSession
9:00–9:15RISC-V Innovation Unleashed: From Design to Verification and BeyondJian Xie · Synopsys
9:15–9:30An Open-Source Pluggable Framework for RISC-V MMU Verification Demonstrated with RiESCUE and Whisper — Validated on Tenstorrent Ascalon and T-Head Xuantie C910Amit Kumar / Arnav Namdev / Viswanadh Karteek Uriti / Sai Teja Ramagiri · Tenstorrent
9:30–9:45RISC-V Multi-core Slice Optimization Practice: SPEC CPU 2017/2026 Performance AnalysisZhiyong Wang · 深圳市中兴微电子技术有限公司
9:45–10:00Security Architecture Design and Implementation for High-Performance RISC-V ChipsLi Ma · Beijing ESWIN Computing Technology Co., Ltd.
10:00–10:15XSV: Practices of a Unified Verification Platform for Complex RISC-V SoCsJiuyue Ma · Beijing Institute of Open Source Chip
10:15–10:45Coffee Break
10:45–11:00Engineering Evolution of OpenHW CVA6 for Modern RISC-V SystemsJunchao Chen · OpenHW Foundation
11:00–11:15RISC-V Hardware Vulnerability Discovery and Exploitation Techniques: Experience Sharing from the Champion Team of the HACK Hardware Security CompetitionsZhiqing Rui · Institute of Software, Chinese Academy of Sciences
11:15–11:30A Portable Firmware for Running RISC-V ACT on Commercial HardwareOwais Farooq · 10x Engineers
11:30–11:45A Cycle-Driven Fine-Grained RISC-V Microarchitecture User-Mode SimulatorChengzhen Meng / Ming Liu · School of Software, Shandong University
11:45–12:00From RISC-V IP to Silicon: System-Level Validation with Si-VAULTGanesh Valliappan · Tenstorrent USA
12:00–13:30Lunch
13:30–13:45A Verification Reference Platform for RISC-V SoC Compute SubsystemGordon Allan · Siemens EDA
13:45–14:00Buckyball: A General-Purpose Foundation for Domain-Specific Chip Design Built on RISC-VHui Wang · 东南大学
14:00–14:15DiffTest-H: FPGA-Accelerated RISC-V Co-simulation -- Breaking the 30 MHz Barrier in High-Performance Processor VerificationKunlin You · Institute of Computing Technology, Chinese Academy of Sciences
14:15–14:30From Heterogeneity to Multi-Die — Virtual Simulation for Efficient RISC-V+DSA Chip DevelopmentHaiyan Hu · 杭州芯芒科技有限公司 (Founder)
14:30–14:45Core Logic Analyzer: Programmable DfD Hardware for Micro-architectural Visibility and ControlSajosh Janarthanam · Tenstorrent Inc
14:45–15:00Wolvrix: An RTL Compilation Infrastructure for Chip Architecture ResearchRuihao Gao / Haojin Tang · Institute of Computing Technology, Chinese Academy of Sciences
15:00–15:152.5D/3D RISC-V Agentic-Acceleration Architecture and an AI-Native Co-Design MethodologyTianyu Jia · 北京大学
15:15–15:30Accelerate High-Performance RISC-V Design Delivery with AI-driven Hyper-convergent Design Implementation MethodologyChao Chen · Synopsys
15:30–15:45RISC-V Memory Ordering Across an AMBA CHI InterconnectUmer Imran · 10xEngineers
15:45–16:00Building a Standardized Extension Framework for DSA: XuanTie FLEXKevin Lin · Alibaba DAMO Academy
16:00–16:30Coffee Break
16:30–16:45From Test Generation to Coverage Closure: A Dynamic Verification Methodology for Complex RISC-V ProcessorsFan Yujie · Synopsys
16:45–17:00Tools as Enablers, Architecture for the Long Run: A Comprehensive Walkthrough of the ArchitStudio Agile Processor Development PlatformZeng Yi · 隼瞻科技（广州）有限公司
17:00–17:15Out-of-Order Agent Flow: Hardware and Software Development Practice of the XiangShan AI ProcessorGuochun Yue · Beijing Institute of Open Source Chip
17:15–17:30Accelerating RISC-V SoC Bring-up and Software Development with Hybrid SimulationHarris Zhu · Shanghai UniVista Industrial Software Group Co., Ltd
17:30–17:45LLM-based RISC-V Virtual Platform & Debug FlowDehao Yang · 思尔芯

Rose Hall 2 · 5FIndustry-Academia Collaboration, Innovation and Entrepreneurship Forum

Co-chairs: Ming Liu (RIOS Lab); Xuan Yang (Linux Foundation APAC)

TimeSession
9:00–9:15How Does Open Technology Turn into Enterprise Adoption? RISC-V Talent Development, Community Collaboration, and Commercialization MechanismsJing Lin · City University of Hong Kong
9:15–9:30From local events to the RISC-V Summits Europe: how the main European RISC-V event came to beChristian Fabre · CEA
9:30–9:45Master RISC-V, AI, and Open Source: Elevating Tech Careers & Honoring Training Leadership with LFOSSAMaggie Cheung · Linux Foundation APAC
9:45–10:00Integrating Industry and Education, Linking Three Zones: RISC-V Advanced Packaging and Intelligent Systems Talent PracticesSam Sam Wang · 上海闵行区先进封装与集成系统研究院
10:00–10:15Stop Reinventing the Core: Building Commercial-Grade Open RISC-V IP Together歐福羅 / Ihsane Tahir / Florian 'Flo' Wohlrab · OpenHW Foundation / Eclipse Foundation
10:15–10:45Coffee Break
10:45–11:00Gathering Intelligence in China, Open Source for the World: Uniting Open Source Forces to Build a RISC-V AI Open Source Innovation and Talent EcosystemWei Fu · Red Hat Limited
11:00–11:15Autonomic Multi-Core Real-Time Debugging for RISC-VAbdullah A. Jassim / Saifuldeen A.Mohammed · University of Baghdad
11:15–11:30RISC-V+AI Talent Development and Enterprise Practice in Open Source CommunitiesWenqi Wang · Beijing ESWIN Computing Technology Co., Ltd.
11:30–11:45Hummingbird E603: A RISC-V Processor from Academic Research to Industrial ApplicationJiandong Qiu · Nuclei System Technology
11:45–12:00The "One Student, One Chip" Project: Designing Your Own RISC-V Processor Chip from ScratchZihao Yu · 中国科学院计算技术研究所
12:00–12:15RvPort: An Intelligent RISC-V Migration Tool — Three Generations from Rule-Based Scanning and AI-Driven Migration to Compiler AssistanceLin Shen · ZTE Corporation
12:15–12:30openKylin RISC-V: Practices in a Collaborative Industry-Academia-Research-Application Innovation EcosystemZhuoheng Li · 麒麟软件

Rose Hall 2 · 5FAutomotive, Industrial and Robotics Forum

Co-chairs: Thomas Xu (StarFive Tech); Yong Yang (WCH)

TimeSession
13:30–13:45Accelerating RISC-V Software Development in Safety-Critical Domains: Challenges, Countermeasures, and Engineering Practices in Automotive Electronics, Industry, and RoboticsNicholas Zheng · IAR
13:45–14:00From Compiler to Runtime Library: Deploying a Functional Safety Toolchain for RISC-V in PracticeShiying Huo · 兆松科技（武汉）有限公司
14:00–14:15RISC-V Core Interrupt Real-Time Enhancement and MCU Hardware Virtualization ArchitectureNeil Fan · Nuclei System Technology
14:15–14:30RISC-V Drives Innovation in Automotive ChipsChangfeng Cao · 湖南紫荆半导体有限公司
14:30–14:45RT-Thread/RISC-V in Practice: Real-Time Control for Automotive and RoboticsBingru Zhang · RT-Thread
14:45–15:00RISC-V Enables Innovation in Software-Defined VehiclesLin Liu · Senior Marketing Manager, Automotive Division, Infineon Technologies; RISC-V Ecosystem Lead, Greater China
15:00–15:15RISC-V-Based Microgrid Edge Collaboration in PracticeSpark Fan · 上海赛昉半导体科技有限公司
15:15–15:30From Open to Reliable: The Evolution of the XuanTie Automotive-Grade Functional Safety ArchitectureWeili Li · Alibaba DAMO Academy
15:30–15:45Architecture Innovation and Engineering Deployment of an RISC-V ASIL-D Automotive-Grade MCULeo Zhao · 上海芯际无限智能科技有限公司
15:45–16:00Efficient flow to achieve ASIL certification for RISC-V for ADAS applicationsItai Yarom · Akeana
16:00–16:30Coffee Break
16:30–16:45Virtualizing Automotive RISC-V MCUs: From Hardware Primitives to a Working HypervisorJosé Martins · OSYX Technologies
16:45–17:00Make Each Error Count: High-Reliability CPU Architectures and Intelligent VerificationZhe Jiang · Southeast University
17:00–17:15Building an Automotive RISC-V Functional Safety Software Ecosystem with Model-Based Design and Generative AIVincent Chen · MathWorks
17:15–17:30The RISC-V isolation toolboxAndrew Dellow
17:30–17:45Reserved slot (to be confirmed)

Demo Talk

Monday, October 19

TimeProgram
10:20–10:35Introduction to the Xuantie Tensor Computing Engine Architecture谢瑞祺 · 达摩院玄铁处理器高级研发工程师
10:35–10:50Microarchitecture Test Generator and Memory-Ordering Checking for RISC-VYahya Sohail · Sr. Engineer, Design Verification, Tenstorrent
10:50–11:05Building Production-Grade Trusted Agent Applications on SpacemiT K3: A Regulatory Perspective刘元弘 · 深圳普适智能有限公司创始人
11:05–11:20Innovative RISC-V Applications in Automotive Scenarios郭广阔 · 奕斯伟计算车载事业部总经理
15:30–15:45LX500: Application Scenarios for a General-Purpose RISC-V AI Computing System许庆伟 · 生态营销负责人，蓝芯算力（深圳）科技有限公司
15:45–16:00StarFive RISC-V CPU Cores and Computing SubsystemsZac · 上海赛昉技术支持
16:00–16:15Mosim + MimicPro RISC-V Agile Development Platform: From Architecture Exploration to Full-System Performance Verification杨一峰 · 上海启芯领航半导体有限公司资深产品经理
胡海燕 · 杭州芯芒科技有限公司创始人

Sunflower Hall · 5FTuesday, October 20

TimeProgram
10:15–10:30Bitra - a user mode X86-64 to RISC-V binary translatorKonstantin Bobrovsky

Wednesday, October 21

Room B-101 · CityUHK ICPRISC-V Hong Kong Day

Co-organizers: City University of Hong Kong; Hong Kong Institute of Science & Innovation, Chinese Academy of Sciences; RIOS

View the full agenda PDF

TimeSession
9:00–9:10Opening AddressProf. Zhao Yang Dong · Head and Chair Professor, Department of Electrical Engineering, CityUHK
9:10–9:20Opening AddressDr. Yinxing Hao · Executive President, Hong Kong Institute of Science & Innovation, Chinese Academy of Sciences
9:20–9:30RV Open Source Community Launch Ceremony
9:30–9:50Plenary AddressDr. Philipp Tomsich · TSC Vice-Chair, RISC-V International
9:50–10:10Keynote SpeechKevin Hilman · BayLibre
10:10–10:30Coffee Break
10:30–10:50Keynote SpeechWei Fu · Principal Software Engineer, Red Hat, RISC-V Ambassador
10:50–11:10Keynote SpeechDr. Hongbin Zhang · Special Research Assistant, Institute of Software, Chinese Academy of Sciences
11:10–11:30Keynote SpeechDr. Xiang Ling · Associate Researcher, Institute of Software, Chinese Academy of Sciences
11:30–11:50Keynote SpeechYuning Liang · DeepComputing
Brian Harrington · Technology Strategist, RISC-V & AI, Red Hat
11:50–12:10Keynote SpeechSajosh Janarthanam · Principal Engineer, Tenstorrent Inc.
12:10–14:00Lunch and Discussion
14:00–14:20Keynote SpeechIulian Arcus · Consulting Principal Software Engineer, DeepComputing
14:20–14:40Keynote SpeechMaggie Cheung · VP, Education, Linux Foundation APAC
14:40–15:00Keynote SpeechKeith Chan · VP, Linux Foundation APAC & CNCF China Director
15:00–15:20Keynote SpeechDong Xu · Head of Software PM, SpaceMIT
15:20–15:40Keynote SpeechFlorian Wohlrab · Head of OpenHW Foundation, Eclipse Foundation
15:40–17:00Keynote SpeechInvited Talks & Industry-Academia Sharing Sessions
17:00–17:10Closing RemarksProf. Ray C.C. Cheung · Associate Provost and Professor, Departments of Electrical Engineering & Computer Science, CityUHK